Optimizing DDR Memory Subsystem Efficiency Part 2 – A Mobile Application Processor Case Study

March 30, 2016 // By Tim Kogel, Synopsys Inc.

Part 1 of this series can be found here.

This whitepaper applies virtual prototyping tools and best practice techniques to optimize the DDR memory subsystem configuration for a specific SoC application. Starting from a hypothetical mobile application processor design, the paper illustrates how to optimize: address mapping, clock frequency, and quality of service (QoS) configuration of a generic DDR memory controller for a given set of use cases and performance requirements.