Following up on their recent progress, EVG is to become a partner in imec’s 3D integration program through a joint development agreement to further improve overlay accuracy in wafer-to-wafer bonding.
Wafer-to-wafer bonding is achieved by aligning top and bottom wafers that are then bonded to form the stacked ICs which can mix heterogeneous technologies (memory, processor ICs etc…)
Many of the alignment techniques and bonding methods for 3D integration have evolved from microelectromechanical system (MEMS) fabrication methods, but for stacked ICs, the alignment or overlay accuracy has to be drastically improved. Accurate overlay is needed to align the bonding pads of the stacked wafers and it is essential to achieving a high yield with wafer-to-wafer bonding.
Firstly, the hybrid (via-middle) wafer-to-wafer bonding technique was improved by using EVG’s high quality bonding system with beyond state-of-the-art integration definition of bonding pads, resulting in a high yield and a 1.8µm pitch, which is significantly better compared to recently published results at recognized conferences such as ECTC and 3DIC reporting 3.6µm pad size.
Secondly, the dielectric (via-last) wafer-to-wafer bonding technique was tackled. This technique requires extremely good overlay accuracy to align the copper pads from both wafers, which are then contacted by through-silicon vias (TSVs). In this case, 300nm overlay across the wafer was achieved.
“By joining forces, we achieved these excellent results on overlay accuracy,” explains Eric Beyne, fellow at imec. “We are excited that we can expand our collaboration with EVG with a JDP and the installation of EVG’s GEMINI FB XT wafer bonder in our cleanroom. The GEMINI FB XT has the potential to further reduce the wafer-to-wafer overlay errors and therefore allow for the development of sub-micron wafer-to-wafer interconnects technologies.”
“Further improving the overlay accuracy for wafer-to-wafer bonding into the sub-200nm range requires optimization of the interaction between the wafer bonding tool and processes as well as pre-and post-processing and the wafer material,” explains Markus Wimplinger, corporate technology development