The module supports flexible clocking with on-board jitter cleaner, and the FPGA connects to DP0-9 and all FMC LA/HA/HB pairs on both FMC sites. The FPGA has an interface to a single DDR4 memory channel (64-bit wide with ECC) which allows for large buffer sizes to be stored during processing. The module has on board 64 GB of Flash, 128 MB of boot flash and an SD Card as an option. The RTM (Rear Transition Module) pinout is compatible with the DESY D1.2 recommendation, for compatibility with a wide range of off-the-shelf RTMs. The Xilinx UltraScale+ XCZU19EG MPSoC FPGA has a quad-core ARM processor, dual-core Cortex-5 and a graphics processing unit. The EG devices have the specialized processing elements needed to excel in next-generation wired and 5G wireless infrastructure, while the ZU19 is the largest device in the range with 1968 DSP slices and 1143k logic cells.
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