Analog startup offers gigasample-per-second ADC core

January 26, 2015 // By Peter Clarke
City Semiconductor Inc. (San Francisco, Calif.) has announced the availability for license of a high-speed analog-to-digital converter core targeting a 40nm CMOS process.

City Semi, founded in 2011, has developed an interleaved successive approximation register ADC with 12 bits of resolution at conversion rate of up to 2.5-GSPS (gigasamples per second). The intellectual property core has been implemented in the 40nm process of United Microelectronics Corp. but can be ported easily to processes at other foundries, City Semi said.

The ADC is suitable for applications in software defined radio, wireless networking, satellite communications, radar, and test and measurement equipment.

The CS_AD122500_UMC40LP design provides exceptional noise performance while consuming less power than other ADCs, City Semi said. Calibration can be implemented on demand, although it does incur an interruption in the output data flow. In order to meet the needs of communications applications, which cannot tolerate interruptions in service, the design also offers background calibration. To simplify design-in voltage references and clock phase generation circuitry is provided onboard. Also, the converter is configurable as either a single, or a dual, for quadrature demodulation.

City Semiconductor has a portfolio of analog designs implemented in nodes ranging from 40nm to 180nm.

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