The work whose results will be presented at IEDM 2016 is based on a device consisting of a two-gate, p-type transistor with an undoped channel, all built on a 300-mm CMOS fab line. The qubit device, explains the paper, is derived from silicon nanowire field-effect transistors and relies on confined hole spins. It consists of a 10nm-thick and 20 nm-wide undoped silicon channel with p-doped source and drain contact regions, and two 30nm-wide parallel top gates, side covered by insulating silicon nitride spacers.
At cryogenic temperatures (circa absolute zero ºK), hole Quantum Dots (QD) are created by charge accumulation below the gates and the double-gate layout enables the formation of two QDs in series, controlled by voltages applied to their respective gates. The first gate defines a quantum dot encoding a hole spin qubit, and the second one defines a quantum dot used for the qubit readout.
Unlike other qubit demonstrations so far, the present research uses regular (albeit cooled down) FDSOI field-effect transistors. The standard single-gate transistor layout is only modified in order to accommodate the second gate for the qubit readout.