While a performance reduction in order to increase endurance could be a critical limiting factor in standard TCAM-based applications requiring many read/write cycles, trading speed for better search/read endurance and better search margin could be sufficient to retain network configuration data in a multi-core neuromorphic chip where long match times (from few tens to hundreds of μs) are required to be compatible with spike length.
So to improve the search margin and search/read endurance, the researchers adopted strong RRAM programming conditions, low search voltage and a limited word length. This came at the expense of lower performance in terms of longer search latencies and lower write endurance, but as the authors emphasized in their conclusion, multi-core neuromorphic computing architectures would not be affected by these problems and could greatly benefit from the RRAM's high density.
In such an application, search operations are frequent, but write operations are few and idle times are long, taking full advantage from the zero standby power consumption of RRAMs while not being affected by the longer search latencies and lower write endurance.
One example cited in the paper is the NeuRAM3 DYNAP-SEL neuromorphic chip (EU H2020 Project running until 2019) whose processing cores comprise multiple TCAM cells per neuron to implement memory-optimized source-address routing schemes. These TCAM cells are typically small and are only programmed at network configuration time.
"Assuming many future neuromorphic computing architectures will have thousands of cores, the non-volatility feature of the proposed TCAM circuits will provide an additional crucial benefit, since users will have to upload all the configuration bits only the first time the network is configured,” explains Denys R.B. Ly, a Ph.D. student at Leti and lead author of the paper.
“Users will also be able to skip this potentially time-consuming process every time the chip is reset or power-cycled.”
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