The partnership ensures companies can be confident selecting the precise RISC-V configuration they require. The combination of Codasip’s IP generation technology and the highly-automated T&VS validated verification flows means that even the most specific configurations can be quickly verified to the highest standards. Such a capability will be essential to fully exploit the flexible, open-source RISC-V instruction set architecture (ISA).
Interest in the RISC-V ISA has grown incredibly quickly and the principal advantages for design teams are the non-proprietary nature of the ISA, the availability of implementations and infrastructure from a range of suppliers and the design freedom allowed by the RISC-V standard.
However this flexibility poses a challenge for verification. Since a wide range of function/power/performance variants are possible, there is no off-the-shelf set of RISC-V validation tests, no single verification testbench, nor even a single verification flow, to fully verify an implementation.
“For customers that are now committing to RISC-V’s verification and validation have become a top concern, and rightly so.”, said Karel Masarik, CEO, Codasip in a company statement. “Codasip’s partnership with T&VS allows our customers to benefit from the outstanding capabilities of T&VS as a verification company and the RISC-V UVM environment automation capabilities intrinsic to our IP.”
RISC-V verification becomes a challenge as particular functionality/performance combination that a design requires is not available in an off-the-shelf configuration. In these circumstances someone has to produce a variant of the design (RTL + Software Development Kit (SDK)) and verify it. This is clearly a challenge for RISC-V providers, whether they are Silicon IP (SIP) companies or service organizations within large companies.
Visit Codasip at www.codasip.com
Visit T&VS at www.testandverification.com
Visit the RISC-V Foundation at https://riscv.org