Conformal logic equivalence checker claims 4X runtime improvement

September 14, 2017 // By Julien Happich
Cadence Design Systems leveraged a massively parallel architecture and adaptive proof technology to deliver an equivalence checking solution four times as fast as previous generation tools.

With the latest advances in logic synthesis at advanced nodes, designers employ aggressive synthesis techniques to achieve power, performance and area (PPA) goals. These advances in both design size and complexity stress equivalence checking proof methods and can result in long runtimes and sometimes inconclusive results. Equivalence checking is a critical step in digital tape-out flows, and the Conformal Smart LEC solution aims to address these issues.

Cadence's Conformal Smart Logic Equivalence Checker (LEC) features a massively parallel architecture that automatically partitions designs and distributes formal proof strategies across multiple machines and CPUs, and can scale seamlessly to 100s of CPUs for improved runtime. This process is fully transparent to the user and does not require manual configurations.
What's more, adaptive proof technology finds the fastest solution to a conclusive proof with minimal user effort. It analyzes each partition and determines the optimal formal algorithm to use to minimize runtime and avoid proof timeouts, especially on designs with complex behavioral datapath components. 
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