Speedcore eFPGAs deliver the highest-performance and lowest-cost hardware acceleration, claims Achronix, with Speedcore custom blocks now allowing functions that traditionally ran slowly and consumed significant resources in standalone FPGA fabrics to be optimised for maximum performance and minimal die area. The company claims that thanks to its Speedcore custom blocks, the area of a CNN-based YOLO object recognition algorithm was reduced by over 40% by optimising the DSP and memory blocks for matrix multiplication. As another acceleration example, large string search functions that require parallel comparator arrays were shrunk by over 90% in die area when implemented in Speedcore custom blocks.
Barrel shifters and bit manipulation structures can be fully implemented in Speedcore custom blocks allowing larger, sophisticated applications in the same area and increasing achievable frequency. The core functionality of a 400 Gbps packet processing data-path running at 800 MHz is implemented in Speedcore custom blocks with the programmable logic managing the analysis and control functionality. Today’s standalone FPGAs cannot support this high throughput for packet processing applications.
Speedcore custom blocks are defined collaboratively by Achronix with its customers through a detailed architecture analysis of acceleration workloads. Repeated functions that are performance and/or area bottlenecks are evaluated as candidates to be hardened into Speedcore custom blocks.