Design platform accelerates the delivery of compute-intensive algorithms for SoCs

May 16, 2012 // By Julien Happich
Esencia Technologies has launched the EScala design platform, claimed to drastically reduce the development time required to implement complex, compute-intensive algorithms on a SoC from months to only days.

According to the company, algorithms that would months to architect, design and verify in RTL can be implemented on an EScala design platform in weeks. EScala uses C/C++ as a design entry language and automatically generates an application-specific programmable core. With EScala, the designer is able to optimize and scale the generated core to best fit the application's area, low power and performance profile. EScala targets algorithms that are currently too demanding to efficiently run on traditional CPUs, like ARM’s Cortex-M or Cortex-R series. A single EScala core offers computational performance that is up to 32 times higher than traditional RISC cores. Additionally the design platform offers built-in support for multi-core architectures that can take on even the most MIPS-hungry algorithms. Many high-end algorithms have very unique memory bandwidth requirements.

EScala supports fully scalable memory interfaces that enable system architects to prevent their cores from being memory bandwidth limited. Migrating algorithms to EScala is easy. The EScala design platform comes with a full software development environment (SDK) for C and C++ that includes an integrated debugger and simulator. Programmers are not forced to use CPU-specific intrinsics or special libraries to get good performance results. The EScala compiler will take care of optimizations. This is a result of Esencia’s proprietary patent pending optimization technology that is used to generate the cores, as well as its run-time code. The EScala design platform generates synthesizable RTL code and related scripts to easily integrate it into an ASIC SoCs. It supports standard bus protocols interfaces like AMBA AHB/AXI as well as Wishbone. These interfaces make it easy to integrate EScala cores with the wide variety of available peripheral IPs. To connect tightly coupled high speed RAM, optimized memory interface protocols are available.

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