Design tools for low cost, low power LatticeECP4 FPGA family

July 16, 2012 // By Paul Buckley
Lattice Semiconductor Corporation has released version 2.0 of the company’s Lattice Diamond design software, the flagship design environment for Lattice FPGA products.

Version 2.0 includes advanced support for the new LatticeECP4 FPGA family, which redefines the low cost, low power, mid-range FPGA market for cost- and power-sensitive wireless, wireline, video and computing applications.

Lattice Diamond 2.0 design software improves the overall user experience by enabling rapid design timing closure and unveils a new, partition-based incremental design flow for LatticeECP3 FPGA devices.  This new design flow will help users preserve design performance and reduce run time after a design change is made.  

The Lattice Diamond design environment enables users to explore design alternatives easily as they target cost-sensitive, low power mid-range FPGA applications – the type ideally suited for the LatticeECP4 family.  Lattice Diamond 2.0 software includes advanced data support for timing, power and packaging based on early silicon characterization of the LatticeECP4-190 device.  In addition to algorithms that help ensure low cost and low power implementation, Lattice Diamond version 2.0 adds a new System Planner tool that enables users to optimize the resource usage of the twelve 6 Gbps SERDES channels offered on the LatticeECP4 devices.  

In addition, the feature-rich power calculator tool provides settings for power save and standby modes, along with pre-emphasis configuration, to accurately analyze and estimate the power consumption of LatticeECP4 designs.  Version 2.0 also enables the generation of the LatticeECP4 device’s DSP blocks: the industry’s only FPGA-based high throughput, double data rate DSP blocks, which are ideal for low cost, high performance RF, baseband and image signal processing.

Achieving timing closure in the shortest amount of time can be a significant challenge as users put more and more functionality into a single FPGA.  When users make a change to their design, they would like the FPGA design tool to preserve some of the critical timing results already achieved and to reduce the overall run time needed to implement the updated design.  Users of LatticeECP3 FPGAs can now use a partition-based incremental design flow to help