The DNA 100 processor targets on-device neural network inference applications spanning autonomous vehicles (AVs), ADAS, surveillance, robotics, drones, augmented reality (AR) /virtual reality (VR), smartphones, smart home and IoT.
The DNA 100 processor delivers up to 4.7X better performance and up to 2.3X more performance per watt compared to other solutions with similar multiplier-accumulator (MAC) array sizes, claims the company.
Neural networks are characterized by inherent sparsity for both weights and activations, causing MACs in other processors to be consumed unnecessarily through loading and multiplying zeros. The DNA 100 processor’s specialized hardware compute engine eliminates both tasks, allowing this sparsity to be leveraged for power efficiency and compute reduction.
Retraining of neural networks helps increase the sparsity in the networks and achieve maximum performance from the DNA 100 processor’s sparse compute engine. This enables the DNA 100 processor to maximize throughput with a smaller array, as evidenced by its ability to achieve up to 2,550 frames per second (fps) and up to 3.4TMACs/W (in 16 nm) of estimated on-device inference performance on ResNet 50 for a 4K MAC configuration.
The DNA 100 processor comes equipped with a complete AI software platform. Compatibility with the latest version of the Tensilica Neural Network Compiler enables support for advanced AI frameworks including Caffe, TensorFlow, TensorFlow Lite, and a broad spectrum of neural networks including convolution and recurrent networks.
The DNA 100 processor can run all neural network layers, including convolution, fully connected, LSTM, LRN, and pooling. A single DNA 100 processor can easily scale from 0.5 to 12 effective TMACs, and multiple DNA 100 processors can be stacked to achieve 100s of TMACs for use in the most compute-intensive on-device neural network applications. The IP also incorporates a Tensilica DSP to accommodate any new neural network layer not currently supported by the hardware engines inside the DNA 100 processor, while also offering the extensibility and programmability of a Tensilica Xtensa core using Tensilica