Eight tips to accelerate SoC physical design at RTL

March 13, 2014 // By Francois Rémond
The growing complexity of modern System on Chip (SoC), the design effort associated with the increasing pressure on silicon cost, and the pressure associated with shortened schedule requirements, makes it essential to use innovative implementation approaches to optimize silicon area and ensure a short and predictable timeline.

Silicon design usually suffers from the disconnection of needs between logical designers and physical architectures. This disconnect leads to costly iteration loops to reconcile incompatible options taken by design teams working in isolation. In this article, we will review the essential points to consider in order to ensure a smooth transition between the logical and physical worlds.

Logical and physical implementation context

Let’s have a look at the situation. At the beginning of the design process, the SoC’s initial representation is captured based on the functional description of the circuit and the logical architecture suitable to achieve the functionality and performance. This is usually expressed as shown in figure 1.


Fig. 1: Typical SoC today.



When it comes to physical implementation – with the assumption that flattening the entire design is not an option due to the size of modern SoCs and the limited capacity of place and route tools at deep submicron nodes – we have to determine a suitable hierarchy for the backend implementation to result in an optimal design.

The traditional approach was to mimic, in the physical domain, the hierarchy inherited from the RTL coming from the logical assembly of the SoC – see figure 2a. The main drawbacks with this approach are the huge complexity of the top-level floor plan, the overall synchronization of the sub block's development and the final timing convergence.


Fig. 2: Different physical implementation strategies of the SoC.




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