A Distinguished Member of Technical Staff at imec, Gouri Sankar Kar published a paper titled "Towards improved data retention in OxRRAM memory devices" of which detailed results have been presented at the 2016 IEDM conference by imec PhD student Michael Chen.
OxRRAM memory, a class of resistive random access memory (RRAM) devices, has already shown its potential for embedded Internet-of-Things devices. The technology is highly scalable, reliable and simple to process, but so far, a poor understanding of the device's data retention failure mechanisms hindered mass production.
An RRAM device in general relies on the formation of a conductive filament in a thin dielectric layer that is sandwiched between two electrodes. When an electric field is applied, the ionic movements and structural changes in this insulating medium cause a measurable change of the device resistance.
Memory operation makes use of two different resistance states: high resistance state (HRS) and low resistance state (LRS). Switching from one to the other can be done by applying an appropriate electric field. The operation which changes the resistance for HRS to LRS is called a ‘set’ process, while the opposite is defined as ‘reset’. The specific resistance state (HRS or LRS) can be retained after the electric field is switched off, and this indicates the non-volatile nature of the RRAM memory.
Now, in the OxRRAM-type of memory, the filamentary switching is based on oxygen vacancy migration in transition metal oxides. The technology shows excellent scalability and reliability, and can be fabricated by using a simple integration flow.
Though, in low-current and fast-pulse programming regimes, a small population of fast-erasing bits (also called retention tails) typically appears. Imec previously associated these retention tails to excess mobile oxygen ions.
During set/reset cycling, these oxygen ions can be injected in or removed from the conductive filament. When the set pulse is insufficient to remove these excess ions from the filament, the ions recombine with oxygen vacancies, and this results in retention failure.
The imec researchers have now extended this analysis by studying the impact of the program history on the data retention properties of the tail bits. Conventional assessment methods are performed on a device-by-device-basis, assuming that retention failures due to fast erasing bits are related to device-to-device differences – arising from e.g. variation in the processing of the memory device.