The 0.13-μm process technology optimizes the structure of transistor and significantly improves ESD characteristics by a factor of four, while the standard deviation is only 1/12 that of the conventional structure. Analysis of 3D simulations has also allowed Toshiba to identify a mechanism for optimizing transistor structure to boost ESD robustness.
Injections of ESD surges, whether from the human body or equipment, have the potential to destroy semiconductor devices, as ESD current flows cause local temperature increases inside silicon. ESD protection devices are required to protect internal circuit. This is especially true for analog power semiconductor devices required to apply 10 V to 100 V, which need a high rated voltage. In this case, ESD protection devices must ensure high current flow, which results in enlarged chip size. Shrinking the size of the ESD protection device is an issue in realizing more compact chips.
Using 3D simulation analysis of an ESD event, Toshiba found out that ESD induced destruction is caused by lattice temperature increase due to the current flowing at the highest electric field point. Modifying the transistor structure, which extending the drain low resistive region to the source direction and suppressing the lateral silicon resistance, shifts the current flow from the bottom of the drain to source direction and detaches it from the highest electrical field point.
This optimized design was found to increase ESD robustness by up to four times and to decrease the standard deviation down to 1/12. In addition, the device size required to ensure a HBM (Human Body Model) of ±2000 V was cut by 68%.