Integrating III-V transistor channels on standard complementary metal oxide semiconductors (CMOS) is the goal of a new three-year, $4.7 million program in the European Union (E.U.) called "Integration of III-V Nanowire Semiconductors for Next Generation High Performance CMOS SoC Technologies" (Insight).
The ultimate aim is to meet the specifications of future 5G and radar systems aiming for wider bandwidth and higher-resolution images, respectively. Besides IBM (Switzerland), the program will be conducted by Fraunhofer IAF (Germany), LETI (France), Lund University (Sweden), University of Glasgow (UK) and the Tyndall National Institute (Ireland).
There will be two phases to the program led by IBM and Lund University, with IBM concentrating on prototyping conventional planar transistors with III-V channels, whereas Lund University will investigate the feasibility of vertical III-V transistor channels.
"First the partners will decide together whether the horizontal or vertical transistor prototypes are the most promising," IBM scientist Lukas Czornomaz told EE Times in an exclusive interview. "Then we will work together to deliver an RF [radio frequency] test circuit, such as a PA [power amplifier] by the end of the three-year program."
The way IBM's process works is by what they call "template-assisted selective epitaxy." They grow an oxide wire where they want the III-V transistor channel to eventually be for a gate-first CMOS-compatible III-V FinFETs on silicon substrates. Next they coat the nanowire with the III-V material so that it only touches the substrate in just a nanoscale or even angstrom-scale area. Lastly, they removed the oxide from inside the III-V coated nanowire, thus resulting in a III-V nanotube transistor channel in precisely the correct position.