The core enables input data rates to be modified to manage systems with multiple clock domains, unifying all signal paths onto a single clock domain. Arbitrary input data rates can be easily matched to support the data rates required for following algorithms such as DEMODS or CODECs. Equally, the core can be used in post filtering applications so that data rates can be optimally set to match the data rate to the output bandwidth.
This makes the core suitable for Digital Signal Process systems development, harmonising over multiple clock domains, clock domain crossing, and algorithm integration that are particularly useful for COMINT, SIGINT, Electronic Warfare (EW), radar, sonar and similar security and surveillance applications.
The architecture uses an Interpolator followed by a Low Pass Filter and a final Decimator stage, leading to the output. This enables the core to change the sample rate of a signal by an integer ratio of L/M, where L is the up-sampling interpolator factor and M is the down-sampler decimator factor. The core can be built as a static configuration (with fixed L and M values) or as run-time programmable variant (where the values for L and M can be modified in real-time). The architecture has an arbitrary internal parallelism and so can support data rates that are limited only by the resources of the FPGA that it is running on. Other key features are a complex wideband input, a high-performance filtering stage and variable bit widths.
RFEL’s Fractional Rate Resampler is available as an evaluation core that allows users to integrate the solution into their wider designs for assessment. The evaluation core operates for 30 minutes, before requiring FPGA reconfiguration and can be simply upgraded to the full version by the purchase of a licence key. It is available to target Xilinx and Altera FPGAs.
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