Industry's first high-performance 4-PLL clock ICs focus on optical networking challenges

May 11, 2011 // By Paul Buckley
Silicon Laboratories Inc. has introduced what the company claims is the industry's highest performance, most integrated clock ICs available to address the complex timing requirements of high-speed optical transport network (OTN) applications. Applying Silicon Labs' patented DSPLL technology, the new Si5374 and Si5375 clocks are the first single-chip timing ICs to integrate four independent, high-performance phase-locked loops (PLLs), providing twice the PLL integration and 40 percent lower jitter than competing solutions.

OTN is a next-generation protocol (ITU G.8251 and G.709) that provides an efficient way to multiplex different services onto optical networks, making it an ideal solution for edge routers, wavelength division multiplexing (WDM) transmission equipment, Carrier Ethernet and multi-service platforms. OTN applications pose complex timing challenges by requiring multiple low-jitter clocks at non-integer-related frequencies. Silicon Labs' quad-DSPLL Si537x devices produce up to eight low-jitter output clocks, simplifying the design of any-protocol, any-port 10G, 40G and 100G OTN line cards.

Each DSPLL clock multiplier can be configured to generate any frequency from 2 kHz to 808 MHz from a 2 kHz to 710 MHz input. This exceptional frequency flexibility reduces the cost and complexity of multi-protocol OTN line cards by minimizing the need for multiple jitter cleaning clock ICs. The Si537x devices' flexible DSPLL architecture simplifies the generation of high-speed PHY reference clocks with industry-leading jitter performance of 0.4 picoseconds, eliminating the need for discrete VCXO-based PLLs currently used in OTU3 and OTU4 applications.

The Si537x devices can reliably lock to gapped clock inputs - a critical OTN line card clock requirement - without separate upstream low-bandwidth PLLs. Other carrier-grade features include SONET-compatible jitter peaking (0.1 dB max) and an innovative hitless switching capability that minimizes output clock phase transients during reference switching, producing a 25x smaller phase transient than competing solutions. Each DSPLL engine features a fully integrated loop filter that supports user-programmable bandwidths as low as 4 Hz, enabling wander filtering in addition to jitter attenuation, configurable on a per channel basis.

The Si5374 device has eight input clocks and eight output clocks while the Si5375 offers four input clocks and four output clocks for applications requiring fewer clocks. With its quad-DSPLL configuration, a single Si5374 clock can generate different frequencies simultaneously, enabling the design to support SONET/SDH, 1/10/100G Ethernet, 1/2/4/8/10G Fibre Channel, 3G/HD SDI video and other protocols simultaneously in the same device.

The Si537x clocks provide a