As established markets such as Smart Phones, Set Top Boxes, Computing and Game Consoles slow many companies are focusing their attention on the newly emerging Medical, Wearable and IoT markets. As the diagram below highlights these markets are predicted to grow at over 9% CAGR in the next few years.
However, to be successful in these markets will demand a markedly different design ethos. The more established markets were driven largely by performance criteria necessitating adoption of leading edge FinFET process technologies to deliver year on year step changes in compute horse power needed to satiate consumer expectations. The newly emerging markets are extremely cost sensitive and, more importantly, power critical. In the case of the IoT market for economic reasons many of these devices will be “fit and forget” hence necessitating extremely low power operation. Inclusion of high capacity Lithium Ion cells is precluded not only on cost grounds, but also on form factor. Addressing this challenge demands innovation from all eco-system partners; Foundries, IP Suppliers and EDA Vendors. Foundries continue to deliver low power variants of cost effective bulk technologies such as Ultra Low Power (ULP) and Ultra Low Leakage (ULL) flavours down to 22nm. There is also growing traction for FDSOI processes at both 28nm and 22nm. It is up to IP suppliers to exploit these advanced process technologies and create robust production worthy solutions capable of low voltage operation. Nowhere is this challenge more pertinent than the creation of low voltage SRAM.
Low voltage design challenges
Operation at low and near threshold voltages needs special attention – not least the re-characterization of the logic cell library to adequately model the increased levels of variation caused by the exacerbation of process variability at low voltage levels. Liberty Variation Format with Moments (LVFM) originally developed to support leading edge process nodes is now being adopted as an expedient way of modelling behaviour as operating voltages are reduced. One area that has remained a challenge is that of embedded SRAM. Whilst the logic may be synthesised to operate at near threshold voltages thereby delivering the requisite power savings the inclusion of SRAM in such circuitry remains a fudge. Underlying this issue is the high-density foundry bit cell.