The company is adamant is has achieved significant progress towards the realization of large-capacity flash memories (100MB or more) to be embedded directly into next-generation MCUs fabricated at the 16 and 14nm nodes.
In the MONOS structure, each memory cell consists of three layers—oxide, nitride, and oxide—on a silicon base, with a metal control gate at the top. The Split-Gate MONOS memory performs its data storage in a thin charge trap film formed on the surface of the silicon substrate, which makes it comparatively easier to deploy it in a fin structure with a three-dimensional structure.
It is highly compatible with 16/14nm logic processes that have the same fin structure. The SG-MONOS flash is said to exhibit excellent charge retention characteristics, not degraded even when the fin structure is introduced.
The challenge when incorporating this fin structure SG-MONOS flash memory cell in a 16/14nm generation MCU is the increase in sample-to-sample variations associated with increasing the memory capacity, notes Renesas who says that for the manufacture of its working prototype, it was able to optimize the process conditions, including the deposition, etching, and ion implantation conditions, for the fin structure, reducing sample-to-sample variations.