Microsemi FPGA tool release with mixed language simulation, uprated debug

April 13, 2017 // By Graham Prophet
Microsemi’s version 11.8 release of its Libero system-on-chip (SoC) software updates the suite of FPGA design tools with enhancements such as mixed language simulation, advanced debugging capabilities and a new netlist viewer; the company is also introducing a free evaluation license enabling users to evaluate Microsemi’s flash-based FPGAs and SoC FPGAs.

The Libero SoC tool suite includes the Mentor Graphics ModelSim Simulator allowing line by line verification of hardware description language (HDL) code. Simulation can be performed at all levels: behavioural (pre-synthesis), structural (post-synthesis), and back-annotated, dynamic simulation. A graphical user interface enables quick identification and debug of problems. Libero SoC v11.8 now includes ModelSim Microsemi Pro allowing customers to simulate in mixed language environments as well as 20% runtime improvement in recent versions of the tool.


Libero SoC v11.8 provides support for VHDL, Verilog and SystemVerilog to target a broad range of intellectual property (IP) designs without concerns about mixing languages. It also includes SmartDebug enhancements, such as the FPGA Hardware Breakpoint (FHB), a capability unique to Microsemi FPGAs. FHBs enable users to set breakpoints in their designs and step by clock cycle, providing significant visibility and enabling significant reduction in debug time.


While breakpoints have been used historically in embedded software, they can now be used to support FPGA logic debug functions. This increases productivity, usability and efficiency of FPGA designs, resulting in faster time to market for customers—particularly in the product validation phase, the longest cycle of product development. These SmartDebug enhancements complement existing debug capabilities which offer a new approach to debug FPGA devices’ status, memory and Serializer/Deserializer (SerDes) transceivers without using an integrated logic analyzer (ILA).


Libero SoC v11.8 includes a number of additional features, including a new netlist viewer providing visibility into different internal structures, new constraints management features offering block flow and an input/output (I/O) advisor, 20% runtime improvements for its SmartTime user interface and Windows 10 operating system support. It comes with a 60-day evaluation license which can be used to evaluate Microsemi flash-based FPGA and SoC reference designs, tutorials and application notes.


Building on Microsemi’s security features, Libero SoC v11.8 includes the company’s Secured Production Programming Solution (SPPS), which generates and injects cryptographic keys and configuration bitstreams to