The HoloLens processing unit (HPU) fuses input from five cameras, a depth sensor and motion sensor, compacting and sending it to the Intel SoC. It also recognizes gestures and maps environments including multiple rooms.
Microsoft described the guts of HoloLens earlier this year, but has not until now publicly detailed its HPU. The company evaluated merchant computer-vision chips including those from Movidius but found none that handled all its algorithms at its performance, latency and power targets.
The TSMC 28nm chip packs 24 Tensilica DSP cores and 8 Mbytes cache into a 12x12mm package with 65 million logic gates. A GByte of LPDDR3 is included in the HPU’s package.
The Tensilica cores were picked in part due to their flexibility. Microsoft added 300 custom instructions to the cores.
“If you can’t add custom instructions, the math density you wind up with is not what you need,” said Nick Baker, a distinguished technologist at Microsoft who described the HPU in a talk at the Hot Chips event held in Cupertino.
The chip uses a mix of standalone accelerators and ones tightly coupled to its DSPs, getting an overall 200x speedup over a software-only version. “We used programmable elements wherever possible and fixed function hardware where we needed it to meet our performance goals,” Baker said.
The code includes a diversity of algorithms with “varying maturity, math, branching and memory-access patterns,” he said.
Separate hardware, software, experience and performance teams worked in parallel. “We took co-design to an extreme with this project,” he said, noting Microsoft has an internal ability to transform simulation tests into emulation routines that can also run on the final hardware.
“This was all going on as Windows 10 was being developed,” he added.
The chip is used in the $3,000 HoloLens developer’s kit released in March. Baker would not comment on any plans