Built on a low power 65 nm process featuring embedded Flash technology, the MachXO2 family delivers a 3X increase in logic density, a 10X increase in embedded memory and more than a 100X reduction in static power compared to previous generations. With the industry’s most robust PLD functionality, ultra low power and new WLCSP packaging, the MachXO2 devices can now address applications previously not accessible to PLDs.
The MachXO2 family leads the industry in providing the lowest power and highest functionality of any PLD family. Now Lattice is extending its lead in the low density PLD market by offering a portfolio of small footprint die/package combinations for the MachXO2 family to be made available throughout 2011, including:
- A 2.5 mm x 2.5 mm 25-ball WLCSP, shipping immediately: Die size-defined BGA with 0.4mm solder ball pitch, providing 19 user I/O in a 6.1 mm 2 footprint
- A 3.2 mm x 3.2 mm 49-ball WLCSP: Die size-defined BGA with 0.4 mm solder ball pitch, providing 40 user I/O in a 9.8 mm 2 footprint
- A 4 mm x 4 mm 64-ball ucBGA: Saw singulated BGA with 0.4 mm solder ball pitch, providing 45 user I/O in a 16.0 mm 2 footprint
- A 8 mm x 8 mm 132-ball ucBGA: Saw singulated BGA with 0.5 mm solder ball pitch, providing up to 105 user I/O in a 64.0 mm 2 footprint
“We have combined aggressive packaging technologies to deliver some of the smallest PLD footprints ever in the programmable logic industry. When these footprints are combined with the superior functionality and ultra-low power available on the MachXO2 devices, we are able to address a new class of applications not previously available to SRAM-based PLDs,” said Shakeel Peera, Director of Marketing for Silicon and Solutions at Lattice Semiconductor. “There is little doubt that consumer device connectivity and space constraints are moving in opposite directions. These new MachXO2 devices will enable new possibilities for digital