Power management is key to 10nm 48 core ARM server chip

August 23, 2017 // By Nick Flaherty
Power management has been a key design consideration for the industry's first 10nm 48 core ARM server chip developed by Qualcomm.

Details of the Centriq 2400 system-on-chip (SoC) and its Falkor processor core were shown at the Hot Chips conference this week. This is the first ARM-based server chip in 10nm, running at 2GHz from a 1.0V supply.

Over half the servers sold by 2020 will be deployed for cloud computing services, according to market researchers IDC, and the processors need to be optimized to address the demand for scalable performance under the unique characteristics of cloud software and services.

Cloud services need to perform well in highly-loaded and multi-tenant environments, and the hardware platform needs to maximize aggregate compute performance while improving the cloud operator’s operational costs, largely driven by the cost of power and cooling.

The Falkor core was designed from the ground up specifically for the cloud datacentre server market. The ARMv8 64bit core has two custom Falkor CPUs, a shared L2 cache and a shared bus interface to the Qualcomm System Bus (QSB) ring interconnect. This modular building block serves as the foundation for the 48-core Centriq 2400 SoC design.

A range of power management techniques were included in the design from the start, such as independent power-state control for each of the CPUs and L2, with entry to and exit from low-power states controlled by hardware state machines for ultra-fast state transitions, and hardware state retention for power-collapsed sleep states with ultra-fast recovery.

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