Quad-core mobile CPU from Samsung described at ISSCC

February 23, 2012 // By Rick Merritt
Samsung gave an early peek at its first quad-core mobile application processor at the International Solid-State Circuits Conference. The unannounced chip is Samsung’s first to use its 32 nm high-k metal gate process and sports advances in performance and battery life over its existing 45 nm Exynos chips.

The chip will come in versions using two or four ARM Cortex A9 cores running at rates from 200 MHz to 1.5 GHz along with a 64-bit ARM Neon media processing block. The cores share a 1 Mbyte L2 cache with a snoop control unit. The chip does not include an integrated baseband.

Samsung is using the latest version of its own graphics unit for the chip. It includes four pixel processors and one geometry engine with a dedicated 128 KByte L2 cache. The graphics support the OpenGL ES 2.0 API and can generate up to 57 Mpolygons/s.

The chip supports two LPDDR2 or DDR3 interfaces running up to 400 MHz for a total memory bandwidth of up to 6.4 Gbytes/s.

Thanks both to the 32 nm process and a handful of power and thermal management techniques, the chip can deliver up to 26 percent more performance overall than Samsung’s current Exynos chip made in a 45 nm polysilicon process. It also can deliver improvements in battery life ranging from 34 to 50 percent, depending on the application.

Samsung said the chip delivers up to 26.3 percent improvements in video frame rates. In a demo, Samsung showed the chip using 48 percent less power on 3-D calculations and 45 percent less power in CPU jobs than the 45 nm chip.

The Samsung 32 nm HKMG process keep transistor and gate leakage nearly to the levels of the company’s 45 nm polysilicon process, much lower than expected for 32 nm polysilicon technology. Samsung tuned the process to a sweet spot somewhere between its potential for delivering 40 percent more performance or a tenth the leakage, said Se-Hyung Yang, a principal engineer for SoC development at Samsung Electronics who presented the paper.

The chip has four independent power domains and several power sub-domains. Each ARM core and up to a half of the cache memory can be turned off or on independently.