In the field of automation, experts speak of a three-part functional hierarchy: sense, think, act. The new microprocessor from NXP is designed to operate the third part of this chain, "Act", explained Ray Cornyn, VP and General Manager Vehicle Dynamic Products at NXP. With four lockstep cores working in parallel at a clock cycle of 800MHz, the device offers the by far highest performance of any comparable microprocessor in that application field, Cornyn claims.
“We see that the shift to next-generation autonomous and electric vehicles is introducing huge challenges to carmakers,” said Ian Riches, executive director in the Strategy Analytics Global Automotive Practice. “Not least of these is the ability to get silicon in hand fast enough and with enough performance headroom to ease the transitions to autonomous and advanced HEV/EV. A car can be extremely intelligent, but if it can’t act safely on a decision, you don’t have a reliable autonomous system at all.”
The NXP S32S processors use an array of the new Arm Cortex-R52 cores, which integrate the highest level of safety features of any Arm processor (see Fig. 1). The array offers four fully independent ASIL D capable processing paths to support parallel safe computing. In addition, the S32S architecture supports a new “fail availability” capability allowing the device to continue to operate after detecting and isolating a failure – a critical capability for future autonomous applications.
NXP has partnered with OpenSynergy to develop a fully featured, real-time hypervisor supporting the NXP S32S products. OpenSynergy’s COQOS Micro SDK is one of the first hypervisor platforms that takes advantage of the Arm Cortex-R52’s special hardware features. It enables the integration of multiple real-time operating systems onto microcontrollers requiring high levels of safety (up to ISO26262 ASIL D). Multiple vendor independent OS/stacks can also run on