The new voltage scalable High-Voltage NMOS and PMOS transistor devices are optimized for various drain-source voltage levels (VDS) from 20V to 100V and provide significant lower on-resistance thus resulting in area savings. Using an optimized 30V NMOS transistor in power management applications instead of a fixed 50V transistor results in an area saving of approx. 50%.
A 60V optimized NMOS device results in 22% less area when compared to a standard 120V NMOS transistor. Foundry customers developing complex High-Voltage analog/mixed-signal applications such as large driver and switching ICs instantly benefit from more dies per wafer.
The area optimized devices are ideally suited for a wide range of applications such as MEMS drivers, motor drivers, switches and power management ICs used in automotive, medical and industrial products.
This latest High-Voltage process extension is an add-on to the company's ”More Than Silicon” portfolio, under which ams provides a package of technology modules, intellectual property, cell libraries, engineering consultancy and services to help customers successfully develop advanced analog and mixed-signal circuit designs based on its specialty technologies.
The complete set of voltage scalable transistors including device layout generator (PCells), simulation models, verification rule decks for Calibre and Assura as well as documentation such as Design Rules and Process Parameters documents can be downloaded by registered users from the company’s secure foundry support server at http://asic.ams.com.
Visit ams at www.ams.com/foundry