SGVC 3D NAND architecture could easily reach 6Gb/mm2 says Macronix

December 06, 2017 // By Julien Happich
At the 2017 IEEE International Electron Devices Meeting (IEDM) that was held in San Francisco, memory manufacturer Macronix International presented test results about its Single-Gate Vertical Channel (SGVC) 3D NAND architecture, from chips built with only 16 layers.

The SGVC technology departs from the typical gate-all-around (GAA) devices proposed by competition for ultra-high-density 3D NAND memories. GAA devices are typically arranged vertically, which makes their critical dimensions more difficult control at high aspect ratios, claims Macronix who first presented the SGVC concept two years ago. Instead, the SGVC 3D NAND makes use of arrays of vertically arranged single-gate, flat-cell thin film transistors with an ultra-thin body, which aren’t as sensitive to critical dimensions variation as GAA devices.


Schematic diagram illustrating the advantages of the SGVC flat-channel device over GAA devices. Oxide-nitride-oxide (ONO) layers and polysilicon keep the channel flat even with a non-ideal vertical etching, giving much greater tolerance to 3D etching performance.

The company's presentation, "A 128Gb (MLC)/192Gb (TLC) Single-Gate Vertical Channel (SGVC) Architecture 3D NAND using only 16 Layers with Robust Read Disturb, Long-Retention and Excellent Scaling Capability” compares its SGVC architecture's merits with other 3D NAND architectures, succeeding in doubling the density of its array design and achieving memory densities on par with competing designs requiring 48 layers.