SiFive raises Series B funding

May 08, 2017 // By Peter Clarke
RISC-V open-source processor developer SiFive Inc. (San Francisco, Calif.) has raised $8.5 million in a Series B round of venture capital funding.

The round was led by Spark Capital with participation from Osage University Partners and existing investor Sutter Hill Ventures. SiFive was founded in 2015 by the inventors of RISC-V – Krste Asanovic, Yunsup Lee and Andrew Waterman – and the Series B round brings the total investment in SiFive to $13.5 million.

SiFive started shipping the industry’s first RISC-V SoC in November 2016 (see SiFive launches first RISC-V SoC ) and announced the availability of its Coreplex RISC-V based IP earlier this month ( SiFive launches commercial RISC-V processor cores ). And in the first six months of the availability of the HiFive software development board more than 1,000 units were bought and delivered to developers in more than 40 countries.

The RISC-V processor architecture developed out of University of California Berkeley as an open-source alternative to such architectures as ARM and MIPS. It is therefore available royalty free but the commercial use of particular instantiations and associated support can still be bound by a licensing contract.

The RISC-V ecosystems includes Google, Hewlett Packard Enterprise, Microsoft, IBM, Qualcomm, Nvidia, Samsung and Microsemi and a growing number of suppliers of development tools and support.

Related links and articles:

News articles:

SiFive launches first RISC-V SoC

SiFive launches commercial RISC-V processor cores

Imperas offers RISC-V processor models

Mixed foursome offers RISC-V development support

Codasip, Baysand bring RISC-V processor IP to market