IC design let aside, there are many processes involved before dies can be stacked together, including the manufacture of Through Silicon Vias (TSV), wafer handling and thinning, TSV reveal etching and Chemical Mechanical Planarization (CMP), then applying micro-bumps to finally stack another wafer or selected know-good dies.
Of course, one way to reduce materials’ costs in these IC-stacking processes is to avoid excess material in the first place and etch minimal layers to reduce the subsequent CMP step (and associated chemical costs).
Wafer handling is a costly issue, especially when the wafer is going to be so thin (down to 50um for the current state-of-the art) that it behaves like a foil and must be securely bonded to a carrier in order to go from one process equipment to the next.
Currently, the norm is to use temporary adhesives, with their own set of issues. They require specific temperature and chemical resistance, yet the adhesives should be removed easily for de-bonding, without leaving a trace. This makes these special temporary bonding adhesives not only costly and their use a yield-issue, but the dedicated machines that dispense, cure, then de-bond and remove the remaining adhesive add their contribution to the multi-million capital expenditure necessary for 3D IC manufacturing.
In the exhibition area, Applied Microengineering Ltd (AML) was showcasing a unique solution to get rid of the adhesive altogether, vacuum-based temporary bonding.
The idea looks amazingly simple. AML has filed a patent for its newly developed vacuum wafer carrier solution, using carriers with etched micro-patterns that allow for a vacuum to be created between the carrier and the wafer to be processed.
“The surrounding seal on the wafer carrier holds the vacuum for up to several weeks”, explained Rob Santilli, CEO of AML, holding a glass carrier to see through the micro-etched suction patterns. “The etched patterns can vary in depth and distribution depending on the wafer’s specific requirements”, added Santilli who