Startup proposes processor on DRAM process

January 24, 2012 // By Peter Clarke
Venray Technology Ltd., (Dallas, Texas) has proposed building a small microprocessor on a DRAM process to save power. The argument that cache transistors outnumber processor transistors on modern processors and therefore a superior design would result from a compromise on the processor and optimization of memory design by building logic in a DRAM process has been made in the past, but has not yet gained traction. It is something Micron Technology Inc., (Boise, Idaho) looked at early in 2000s.

Venray, founded in 2007, argues that such a processor can reduce power consumption to between one-fifth and one twentieth of an ARM or Intel Atom processor. Venray also claims a fifth to tenth the cost compared to ARM or Intel chips. At the same time Venray is claiming performance benefits from being able to connect CPUs and on-chip main memory through ultra-wide buses.

However, it is not clear for what applications the Venray architecture is optimized although the company writes on its website of improving mobile phone and tablet computer size, weight and performance.

Venray has developed the TOMI architecture (Thread-optimized Multiprocessor Instruction) and designed the Aurora SoC and Borealis chips but does not appear to have taken them to silicon.

Aurora is a 4-core processor with 64-Mbytes of memory. Borealis is an 8-core processor with 1-Gbyte of memory. The four-core Aurora has a projected cost of less than $1. Aurora has been designed for a 110-nm DRAM process and 500-MHz clock frequency CPUs would consume 23-mW each, Venray claims.

The primary disadvantage of designing logic in a memory process – and one reason it has not been adopted before – is because DRAM processes traditionally only offer 3 layers of metal, not enough to implement most legacy processors. Logic processes typically offer 10 or more layers of metal.

Other disadvantages that Venray states it had to contend with included the fact that DRAM transistors are typically 20 percent slower than logic processes at the same node and DRAMs are sensitive to high current spikes. As a result Venray uses differential signaling in the designs.

Venray's TOMI architecture has been designed to be simple, to save power and be implementable in three-layers of metal and also perform well on big data sets. The Borealis core has just 22,000 transistors, Venray states. The Aurora core has 18.6K transistors and its 79 instructions are implemented on a two-stage pipeline.

The company was