If you have designed blocks in sub-micron manufacturing process technologies you realize that supply voltages make circuit designs difficult. In the newer technologies, the supply voltage continues to shrink. So how does an analog designer design on technologies where the maximum core voltage is dropping to the one volt region. The immediate response may be to use higher voltage transistors as a higher 5V or 3V transistor is usually available. However, using the higher voltage transistor has its own drawbacks. Many of the limitations from using higher voltage transistors become more apparent if the analog block being designed is high performance or requires speed. In addition, once a block is designed using the higher voltage devices the outputs of these blocks must interface with other blocks that may not be designed at the higher supply voltage.
This can become very problematic. So what to do? Many designers opt to use the lower voltage devices that have the speed that is needed but will need to accommodate for the smaller voltage supply.
What does this mean? Because of the smaller supply voltages designers are forced to operate the transistors at the edge of linear mode of operation. As you may know, if the transistor enters into this linear mode the gain, output impedance, Ft, and other parameters change. Most of the time this is not the desired result. Therefore, designers must understand where it is acceptable to bias their transistors to avoid moving into the forbidden realm. This is the topic I would like to discuss.
Some of the important parameters to monitor when setting biasing conditions for transistors are the following:
This list is by no means an exhaustive list but does highlight some of the most important analog metrics to watch for when designing analog blocks. These metrics and the allowable range will be different