Three pillars for Leti's post-CMOS plan : Page 2 of 4

July 18, 2017 // By Peter Clarke
French research institute Leti has a post-CMOS plan that is driving research decisions. That plan rests on three broad pillars and some more specific developments such as neuromorphic and quantum computing.

"We have removed a lot of the road-blocks and worked with Qualcomm and Applied Materials on stacking with 14nm FDSOI structures. Two- and few-layer integration through the use of copper-to-copper bonding and through-silicon-vias (TSVs) can be useful for developments such as memory-over-CMOS or image-sensor over CMOS, Reita said. "Multilayer monolithic integration is really for the ultimate 3D," he added.

One challenge yet to be truly overcome is generalizing 3D design. EDA is essentially based on a two-dimensional paradigm and is set up to optimize for 2D performance against area, which also reflects cost or production. Some of the benefits of 3D design, such as putting memory close to logic and dramatically increasing bandwidth, are not supported in automated design tools.

"We did work with Georgia Tech on place and route and we had collaboration with Mentor Graphics," said Reita. It is partly a "chicken-or-the-egg" problem, he said. The EDA industry is reluctant to invest in developing tools unless there is a market and chip developers are unable to start making 3D circuits in big volumes without tool support.

"We have some internal tools but thinking in 3D is not so easy. One of the things you find is that when comparing 2D and 3D design partitions the average wire length is about the same. But what you do is reduce the length of the longest wires, you cut off the long tail of 2D wire length distribution, which is a good thing," said Reita.

If the general case for 3D circuitry has been slow to develop it is now starting to emerge in specific cases. And what about quantum computing?

Double-gate qubit built on 300mm wafer 28nm FDSOI. Source: Leti.

"For the last 40 years or so the research into quantum computing focused on quantum wells in III-V compound semiconductors. But in the last 10 years or so the research has started working on silicon. Leti has reported a qubit built using 28nm FDSOI on a 300mm wafer; in fact a pair of quantum devices coupled by a tunnel junction."

The use of silicon holds out the prospect of more affordable quantum computing and hybrid quantum/conventional computing because of potential compatibility with CMOS. "And silicon quantum computing can reuse a lot of the engineering from nano-electronics," said Reita. However, quantum computing is unlikely to replace conventional computing or even achieve ubiquity in the near future, said Reita. This is mainly because for most materials it requires extreme low temperatures of less than 100mK to achieve sufficiently long electron-spin life times for quantum computing to take place.

Unfortunately, below about 4K CMOS tends to stop working with imbalances between the electron and crystal lattice temperatures, Reita said. "Dopants freeze and connections can become either superconducting or highly resistive." So Leti is also working on cryogenic CMOS to ensure to interfaces between conventional computing and quantum computing are possible.

The challenges include moving from single and few qubits to multiple qubits and an understanding of how to limit the level of noise that requires quantum correction, Reita said. "In five years' time we hope to have a quantum machine doing meaningful computing," said Reita.

Next: Neuromorphics


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