Leti is part of the NeuRAM 3 European collaborative research project that is developing the Dynamic Neuromorphic Asynchronous Processor Scalable-Learning (DynapSEL) for implementation in 28nm FDSOI. The design taped out in November 2016 and silicon is expected back this month of July.
Floor plan and specifications of DynapSEL chip. Source: Institute of Neuroinformatics of University of Zurich (Prof G.Indiveri) and NeuRAM3 project
For now DynapSEL has an SRAM on board. A lower-power version with non-volatile memory is due for delivery in the second phase of the program and by the end of 2018. As to what sort of non-volatile memory Reita said the decision is not yet final.
There are choices with different levels of maturity, ease of integration, and suitability to synapse behaviour. Filamentary OxRAM, such as hafnium oxide, is a favorite for reasons of ease of manufacturing integration, said Reita. Conductive bridging RAM (CBRAM) is a design favorite because voltage levels match CMOS and it is the lowest current. Finally there is chalcogenide-based phase-change memory (PCM), which appears to be an industry favorite with Intel now introducing its 3D Xpoint memory, said Reita.
To conclude Reita pointed out that challenges with Moore's Law scaling over the past few years is increasing the opportunities for research but also prompting institutes to focus – and in part gamble – on where they can add the most value. Rieta is pleased that some of Leti's choices made four years ago are now starting to pay off.
"The way we decided to go now seems to be more widely accepted. Shrinking is used up for the main part but there are a lot of possible alternatives. We are coming into an era of system optimization again. And that is why system companies are re-aggregating things."
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