TRACE32 now supports MIPS Release 6 CPUs including the new M-class M6250, the first embedded-class MIPS CPU to incorporate the MIPS On-Chip Instrumentation (MIPS OCI) flexible on-chip CPU debug architecture. Companies can use MIPS OCI to ensure the lowest possible risk and impact on their debug process for highly-integrated heterogeneous SoCs.
TRACE32 enables simultaneous debug of the multiple CPUs in a design with ‘mixed mode’ trace streams. Users can view the interleaved results in a single trace window, with a system-level timestamp to help align the streams. Extended trigger logic enables cross-triggering between the CPU trace logic to make it even easier to debug processor interdependencies.
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