Xilinx lays grounds for 16nm FPGAs with new architecture

March 03, 2014 // By Julien Happich
FPGA manufacturer Xilinx who announced last year some test-chips on TSMC’s 16nm FinFET process, and who is already using 2.5D packaging for its multiple-die 28nm FPGAs, is laying grounds for heterogeneous multi-processing on 3D ICs.

The company announced its UltraScale Multi-Processing Architecture for what it says will be the industry’s first All Programmable MPSoCs.


“Moving from 28 and 20nm to 16nm, we had to deploy a new architecture that would truly support heterogeneous multi-processing” explained Steve Glaser, Senior VP of Corporate Strategy & Marketing at Xilinx who hinted at more dedicated acceleration engines, partly in software and partly in distributed hardware blocks.


In principle and to be future-proof, the new architecture could also make room for truly heterogeneous die stacks for cost-efficiency too.


The company looks at compute-intensive yet energy-efficient designs, in wireless and wired communications, in data centers, in M2M, in smart-vision.

These fields call for data pre-processing, evolving video-processing algorithms, analytics. With its UltraScale MPSoC architecture, the company will provide processor scalability from 32- to 64-bits with support for virtualization. Scalability includes CPU, interconnect, peripherals, processing engines and address space to Terabytes, according to Xilinx’ preliminary specs.

 

Glaser would not reveal how the fabric will be organized, but said that various flavours of the 16nm Zynq UltraScale MPSoCs would be available to account for the different processing requirements of these vertical markets, with different grouping options of the hardware accelerators to deliver “the right engine for the right tasks” as their promotional brochure says.