Under Xtacking addressing and I/O circuits are made on a separate wafer to the vertically stacked NAND cells and then bonded to them face-to-face through millions of vertical vias at the wafer-scale to complete the memory components.
Conventionally peripheral circuits are set down first and NAND flash transistors set down later. To withstand the subsequent process steps the peripheral transistors have to be higher voltage which in turn limits I/O speed.
Splitting the manufacturing on to two wafers with different processes results in superior I/O performance and a smaller footprint, YMTC claims, but at the expense of extra complexity in manufacturing. Bonding at the wafer scale limits the overall cost of this extra step, Yangtze said, although it does require die slicing after the via bonding step. The step does allow Yangtze to use an optimum logic process for the I/O.
"At present, the world's highest 3D NAND I/O speed is targeting 1.4Gbps while the majority of the industry is offering NAND I/O at 1.0Gbps or below. With our Xtacking technology, it is possible for NAND I/O speed to reach up to 3.0Gbps, similar to I/O speed of DRAM DDR4," said Simon Yang, YMTC CEO, in a statement.
In conventional 3D-NAND architecture, the periphery circuits take up 20 to 30 percent of the die area. As 3D-NAND technology progresses to 128 layers and above, the periphery circuits will likely take up more than 50 percent of the total die area.
The approach also allows for customized NAND flash memories by the inclusion of additional IP in the peripheral circuits.
YMTC said it has developed a second generation of 3D-NAND memory using the Xtacking approach and plans to go into volume production in 2019 aiming at smartphone, personal computing, data center and enterprise applications. The company of layers in its next 3D-NAND was not announced but the company produced a 32-layer 3D-NAND flash chip in 2017 (see Yangtze makes 32-layer NAND flash) with 64-layers as the next obvious stopping off point.