Moortec: Embedded PVT monitoring from 40nm to 7nm

January 18, 2018 //By Moortec
Moortec: Embedded PVT monitoring from 40nm to 7nm
This white paper discusses challenges of design at 16nm and below including maufacturing variability, high current density, self-heating and excessive guard-banding. Also temperature inversion of performance below 40nm node. The use of performance, voltage and temperature (PVT) monitoring helps cope with complexity and the paper discusses multiple ways it can be employed.
Company: 
PVT, monitor, design, IP

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