The internal chip arrangement gate driver of ADuM3223 (Figure 1) exhibits one example of chip placement avoiding breakdown of the electrical isolation during extreme electrical overstress.
Destructive Test Simulating Worst Case Inverter Failure
A test circuit with two voltage levels of 385 V and 750 V was built to emulate real power inverter conditions. The voltage level 385 V is very common in a system requiring power factor correction with a 110 V/230 V ac grid. The voltage level of 750 V is common in high power inverters used in drive applications using switches with a rated breakdown voltage of 1200 V.
In the destructive test, one inverter leg, consisting of a power switch and an appropriate driver, was turned on until the switch failed. The waveform during destruction was recorded to determine the energy level flowing into the gate driver chip. Several protection measures were investigated in order to limit the destruction energy flowing into the gate driver circuit. Several types of IGBTs and MOSFETs were used in the destructive tests.
Test Circuit with Controlled MOSFET/IGBT Damage
For the IGBT/MOSFET driver electrical overstress tests (EOS-test), a circuit very close to real-world conditions was setup. The circuit included capacitors and resistors reasonable for inverters in the power range of 5 kW to 20 kW. For gate resistor Rg, axial type, 2 W rated power metal resistors were used. One blocking diode, D1, was applied to avoid energy reversing from the high voltage circuit into the external power supply. This also reflected realistic conditions, as floating power supplies include at least one rectifier (that is, bootstrap circuit). The high voltage supply, HV, charged the block electrolyte capacitance by a circuit including a charge resistor, Rch, and one switch, S1.
For the EOS-test, a turn-on signal of 500 µs was applied to control input VIA or VIB. This turn-on signal, which was transmitted via the microisolation, caused a short condition and destruction of the power transistor, T1. In some cases, transistor package explosions were observed.
Four power switch types at two voltage levels were used to simulate inverter damage. The first test for a particular switch type was performed without, and then with, a power limiting circuit. To limit energy flowing into the driver circuit during the damage phase, Zener diode Dz (BZ16, 1.3 W) was applied directly to the driver output pin for some tests. Different values of gate resistors have been investigated as well.