Power Limit for Insulation Capabilities of Modern IGBT/MOSFET Gate Drivers: Page 3 of 6

February 21, 2019 //By Bernhard Strzalkowski, Analog Devices
Submitted by hammerschmidt on Thu, 02/21/2019 - 09:32
Power Limit for Insulation Capabilities of Modern IGBT/MOSFET Gate Drivers
This article investigates a gate driver’s isolation withstand performance through the intentional destruction of IGBT/MOSFET power switches.

Figure 3. Layout of the EOS circuit ADuM4223 when used to measure the impact
of power switch destruction on isolation withstand.

 


Figure 4. Layout of the EOS circuit ADuM4223 when used to determine the energy limit for isolation withstand.

 


Figure 5. An EOS circuit ADuM4223 in worst case, when the energy is applied directly
to the input and output chips.

Test Circuit for Direct Gate Driver Circuit Damage without Energy Limit

Another test simulating the worst-case condition was performed, wherein the destructive energy was applied directly to the input and output chips of the gate driver. During this destructive test, the fully charged bulk capacitor was directly connected to the output pin of the gate driver (Figure 4). This test exhibited the worst possible overstress, and thus examined the isolation withstand capability. The energy flowed directly into the driver circuit while the gate resistor was the only power limiting device. The relay, S2, coupled the high voltage into the gate driver output circuit.

Design category: 
Power components

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