Power Limit for Insulation Capabilities of Modern IGBT/MOSFET Gate Drivers: Page 5 of 6

February 21, 2019 //By Bernhard Strzalkowski, Analog Devices
Power Limit for Insulation Capabilities of Modern IGBT/MOSFET Gate Drivers
This article investigates a gate driver’s isolation withstand performance through the intentional destruction of IGBT/MOSFET power switches.

By comparing test 2 with test 3, and test 3 with test 4, the driver damage energy can be estimated. A very interesting conclusion was provided by tests 5 and 6: super-junction MOSFETs seem to cause significantly lower energy levels flowing into the gate driver than one IGBT having the same power rating. The purpose of tests 9, 10, and 11—with unlimited energy flow into the control and driver chip—was to investigate the isolation withstand performance in worst-case scenarios.

Different Destruction Behavior of a MOSFET vs. an IGBT

The destructive tests showed different waveforms experiencing power switch damage. Figure 6 presents the waveforms for a superjunction MOSFET. The time period between turn-on and chip destruction was approximately 100 µs. Very limited current flowed into the driver chip, which withstood the overstress. For the same test condition, a standard MOSFET caused significantly higher gate current and overvoltage resulting in driver destruction, as presented in Figure 7.

Analysis of Chip Damages

Partial encapsulation of gate drivers shows similar chip damages for different switches and different test conditions. Figure 8 shows the damage for a P-MOSFET based output driver stage in test 8 (Table 1). The test at a bulk voltage 750 V caused an IGBT explosion, as well as the destruction of limiting devices Rg and DZ; however, only a small molten area very close to the bond wire of pin VDDA is visible. The gate overcurrent during the damage phase flowed via the intrinsic diode of P-MOSFET into the 100 µF capacitor. Due to current crowding, the area close to the bond wire melted. No further driver chip damage and no isolation damage on the control chip was observed. Figure 9 shows molten areas during test 9, where a high voltage of 150 V was directly applied to the driver chip. The electrical isolation of the control chip survived this extreme overstress test.


Figure 8. A gate driver chip photo showing the damaged area during test 8 (ADuM4223 #1).
Only the appearance of a small molten area on the output chip occurred. No damage of the isolation
was detected.

 


Figure 9. A gate driver chip photo showing damaged areas during test 9 (ADuM4223 #2).
Extreme electrical overstress did not destroy the control chip. No damage of the isolation was detected.


Figure 10. A gate driver chip photo showing damaged areas during test 10.
The unlimited energy applied to the output driver destroyed the circuitry; remarkable molten area.
However, no damage of the isolation was observed.

The worst case on the primary side exhibits the application of excessive supply voltage to the control chip. Thus, in test 11, a supply voltage of 15 V was applied to the VDD1 pin (Figure 5), which significantly exceeds the absolute maximum rating of 7.0 V. The photo in Figure 11 shows molten areas in the chip in the vicinity of the VDD1 pin.


Figure 11. An input control chip photo showing damaged areas during test 11.
The energy applied to the circuit created a very limited molten region surrounding the VDD1 pin. No damage
of the isolation was observed.

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