Security-hardened reset domain crossing circuit: Page 5 of 5

April 11, 2019 //By Satyanarayana Murthy Madimatla, Sandeep Jain, Vivek Sharma (NXP Semiconductors)
Security-hardened reset domain crossing circuit
While we focus on various security features of modern automotive designs, reset interface could be offering a favorable surface to the attackers, if not handled appropriately.

Some previous articles like [1] discuss reusing EDA checks build for ensuring power boundary crossings to identify & verify reset crossings. However, [1] just identifies/flags violating condition, whereas our implementation proposes a circuit based robust mechanism to address RDC. Another known design [2] presents a set of solutions to handle RDC crossings that proposes an intelligent method to hold the destination data using clock gates to avoid corruption from source domain. Another work [3] proposes multiple techniques to handle RDC crossings in the design and various verification techniques. The proposed technique elaborates on an efficient practice to control the destination clock, rather than directly gating destination clock as in [3] and the drawbacks of implementing a simple clock gating are also explained. The solution is further hardened for protection against any security attacks.

We have proposed an efficient circuit implementation to safely handle RDC crossings in a multi-reset design by gating destination clock based on reset generation request from reset generation module. A comparative study has been presented against some of known work to ensure the robustness of our implementation.

References:

  1. DDeep Shah, Namit Gupta, Mohamed Shaker Sarwary, Reset Domain Crossing Management using Unified Power, US20180004876A1, 1/4/2018.
  2. Article www.embedded.com - Dealing with SoC metastability problems due to Reset Domain Crossing
  3. Multiple Reset Domains Verification Using Assertion Based Verification - https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8203467

About the authors:

Satyanarayana Murthy is part of security IP development team in Automotive Division of NXP Semiconductors. He was responsible for supporting DFT methodologies in Digital IP team at Freescale Semiconductors, India. He received his master’s degree in Microelectronics and VLSI from Indian Institute of Technology Roorkee, India in 2015.

Sandeep Jain is responsible for security IP development in NXP´s Automotive Business Unit. Before his current assignment, Sandeep worked as SoC design lead for an automotive design. Before that he was managing DFT activities for all Freescale automotive designs at India design centre. He received his bachelor’s degree in Electronics and Communications Engineering from MDU University, India in 1999.

Vivek Sharma is part of Security IP development team in Automotive Division of NXP Semiconductors. He was responsible for front-end Design Verification in Digital IP team at NXP, India. He received his MTech degree in VLSI System Design from National Institute of Technology Warangal, India in 2006.

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