Ultra-low power microcontrollers enabling energy harvesting applications: Page 3 of 7

June 19, 2019 //By Graeme Clark, Renesas Electronics
Ultra-low power microcontrollers enabling energy harvesting applications
In the aftermath of the Fukushima nuclear disaster in Japan, the Japanese government set up the LEAP (Low power Electronics Association and Project) initiative. This has the express aim of developing new, ultra-low power technologies to reduce energy consumption in a wide range of applications across the consumer and industrial market in Japan.

This combination of integration and power consumption will make devices developed on this process ideal for energy harvesting applications. It is also likely to reduce the overall energy demands by up to 10 times compared to a device using the traditional CMOS bulk silicon process.

One of the huge breakthroughs in the development of this technology has been the ability to realise a hybrid silicon structure. As this combines the benefits of the new SOTB process and the existing standard bulk silicon technology on the same design, we can utilise the strengths of both technologies on the same device and provide microcontrollers with embedded flash memory.

The use of the hybrid structure means we can use the new ultra-low power SOTB technology for the gates used in the kernel area. Key logic components such as the CPU and peripherals can be implemented and will use the lowest possible power. We can still use standard bulk silicon gates for features such as the I/O ring and analogue components, where high voltage drive may be required. This means that designers can easily work with these new microcontrollers as they will have similar electrical characteristics to today’s existing microcontrollers.

Figure 2 illustrates this hybrid architecture.

Figure 2: SOTB’s hybrid structure

This diagram also shows some of the benefits of the SOTB gate structure. In a traditional CMOS bulk silicon gate design, we must inject channel impurities or dopant atoms into the silicon during the manufacturing process, which enables the gate to conduct when required. The number of atoms injected into each gate is extremely hard to control accurately, so the gate threshold characteristics can vary greatly across a device. This is especially a problem with smaller silicon geometries when the number of atoms involved is extremely small, sometimes in the region of 100 individual atoms. This means that there can be a significant variability in the number of dopant atoms in each gate, resulting in a significant variability in the switching characteristics of each gate within the device.

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