SOTB avoids this problem by using a dopantless channel design in which the characteristics of the gate are controlled by the extremely thin oxide layer within the gate. Using modern process technology, this is extremely well controlled and is therefore extremely repeatable across the device.
This means that the variation in threshold voltage between each gate is much lower than with the traditional bulk silicon gate design. As will be seen in a moment, this reduction in the variation of the threshold voltage between gates on a SOTB device allows us to greatly reduce the operating voltage and hence the energy used to switch the gate. This limit in the variation of the threshold voltage between the gates on the device also has several other significant benefits, such as a reduction in the noise generated between matched pairs of gates within the device.
The noise reduction also has an impact on the analogue performance of the device. Due to the lower internal noise, the analogue performance is significantly enhanced, allowing the integrated analogue components to provide higher performance than on a standard CMOS bulk silicon design.
The thin Silicon on Isolator (SOI) layer also has some additional benefits, as it provides extra protection from errors causes by cosmic rays. As such, the software error rate on these devices is significantly lower compared to similar devices on the same process node.
Figure 3 illustrates another benefit of the SOTB technology: the ability to apply a negative back bias voltage to each gate. This allows us to manipulate the switching thresholds of each gate on the device, either individually or across the total device.
Figure 3 (left) illustrates the design of the SOTB gate with the back-side gate used to control leakage, the SOI layer and the dopantless channel. This enables the reduction in gate variability and so allows for the extremely low active current.
Figure 3 (right) shows a comparison between an SOTB device and a device made on a standard bulk silicon process.
The graph on the left-hand side of Figure 3 shows the threshold voltages for both a standard CMOS bulk gate and an SOTB gate. The red line on this graph shows the range of switching characteristics for a typical device implemented on a bulk silicon process. In this case, we show the variation in switching threshold between the 1 million individual transistors on the test chip. The diagram shows that the best gates will switch at around 0.3v, while due to the inherent variability of the process, the worst gates will switch somewhere in the region of 0.7v. In order to guarantee the operation of every gate on the device, we must therefore operate at voltages significantly above 1.0v. This of course has a direct impact on the power consumed by the module.