Ultra-low power microcontrollers enabling energy harvesting applications: Page 5 of 7

June 19, 2019 //By Graeme Clark, Renesas Electronics
Ultra-low power microcontrollers enabling energy harvesting applications
In the aftermath of the Fukushima nuclear disaster in Japan, the Japanese government set up the LEAP (Low power Electronics Association and Project) initiative. This has the express aim of developing new, ultra-low power technologies to reduce energy consumption in a wide range of applications across the consumer and industrial market in Japan.

The blue line in Figure 4 shows the characteristics of the SOTB gate with the huge reduction in variability and the narrow range of switching characteristics that can be achieved with this process. Devices based on the SOTB process can safely run at much lower voltages and guarantee that every gate will operate correctly, resulting in a huge reduction in the value of the active power consumption.

The green line in Figure 4 shows the result of the back bias being applied. We can control leakage on individual gates. In other words, we can place part or all of the device into an extremely low leakage state, which greatly reduces standby current.

The result of this new process is that we can develop a new generation of microcontroller products. These will combine the best qualities of both smaller geometry technologies with their high levels of integration, low active current and larger geometry, low leakage current devices.

Renesas have now finished development of the first microcontroller using the SOTB process. The use of the SOTB process allows us to produce a device with a unique combination of performance, integration and power consumption. The first device combines a Cortex M0+ Core running at up to 64 MHz with a high level of peripheral integration and up to 1.5 Mbytes of flash and 256 Kbytes of on-chip SRAM.

The use of the Silicon on Thin Buried Oxide technology on this new device has resulted in some unique low power characteristics. The first device has the following features and future devices using this process could offer even lower power consumption.

  • Active current of 20 µA /MHz
  • Standby Current of 200 nA
  • ADC operation 3 µA @ 32 kHz
  • 256 Kbyte SRAM with 1 nA / Kbyte standby current

The first device to use the new SOTB process is the Renesas R7F0E017. The block diagram in Figure 4 provides an overview of its features.

 


Figure 4: the first microcontroller using the SOTB process

The new Renesas R7F0E017, with its unique combination of large on-chip flash memory and on-chip SRAM along with ultra-low power consumption levels, will be ideal for a wide range of applications. These include applications that cannot use a battery or remote power source and energy has to be supplied from the environment.

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