$1.6bn for US advanced chiplet packaging R&D projects
The National Institute of Standards and Technology (NIST) is opening a competition for $1.6bn funding for four advanced packaging R&D plants under the US CHIPS Act.
The NIST CHIPS National Advanced Packaging Manufacturing Programme (NAPMP) includes chiplets as well as EDA tools as well as equipment, process Integration as well as Power Delivery and Thermal Management. This also includes connector technology with photonics and Radio Frequency (RF) as part of the 2024 IEEE Heterogeneous Integration Roadmap
In addition to the R&D areas, the programme is expected to include a specific opportunity for prototype developments in high-performance computing and low-power systems needed for AI.
The technical focus and R&D goals of the programme are expected to be informed by recent industry roadmaps, which share the common theme that emerging applications like high performance computing and low power electronics, both needed for artificial intelligence (AI), require leap-ahead advances in microelectronics capabilities, including advanced packaging.
The exemplar applications are likely to focus on areas such as high-performance computing and low-power systems needed for AI. Prototypes should be designed to demonstrate and validate research advances and new packaging flows resulting from projects supported by the programme
CHIPS R&D anticipates awarding a total of $1.6bn in cooperative agreements and other transaction agreements with $150m per award, although multiple awards for projects varying in scope and funding amount are expected with five years per award.
While co-investment will not be required, CHIPS R&D will give preference to applications that demonstrate credible co-investment commitments.
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The aim is for NAPMP activities, coupled with CHIPS manufacturing incentives, will establish a vibrant, self-sustaining, profitable packaging industry in the US. This would be used with advanced node chips manufactured in the US and abroad can be packaged in appropriate volumes within the US.
Advanced packaging and related capabilities, such as heterogeneous integration, are designed to increase all aspects of system performance by linking multicomponent-assemblies with large numbers of interconnects to achieve a degree of integration that blurs the line between chip and package.
Another driver is demonstrating functionality in prototypes to provide evidence for new capabilities, increased efficiencies, lowered production costs, reduced environmental impact, or other benefits resulting from research advances.
For power delivery and thermal management, the R&D will expect new thermal solutions for implementation with advanced substrates, 3D heterogeneous integration (3DHI), and other design aspects – to reduce hotspots, maintain thermal targets, and enable reliability in multilayer stacks without constraining connectivity. This will require innovative approaches for delivering power at high density with efficient voltage regulators and dynamic power management schemes for 3DHI devices, including modular designs and devices for use with a variety of chiplets.
Validated, higher fidelity models and accelerated learning using artificial intelligence and machine learning (AI/ML) will be used to accurately predict power and thermal distribution across chiplet stacks and enable advanced system design and evaluation as well as vertical heat extraction, local heat spreading, advanced methods for active and passive cooling of 3DHI devices to reliably operate at higher power density, wide bandgap chiplets for 3DHI, and advanced materials and architectures to achieve specific thermal and power goals such as low-resistance thermal interfaces.
The links between the packaged assemblies may be via flexible wire, such as serializer/deserializer (SerDes) with or without repeaters; wireless, including RF; or low-loss photonics via optical fibre arrays. RF transceivers and optical engines are expected to be provided using chiplet- based technology or embedded directly into the advanced substrates.
“The CHIPS R&D facilities launch is an exciting milestone in the implementation of President Biden’s CHIPS & Science Act. This will help build the R&D infrastructure America needs to lead on advanced manufacturing for decades to come. President Biden is determined that semiconductor manufacturing will thrive in America after it was neglected for far too long,” said Lael Brainard, National Economic Advisor.
“Standing up domestic assets for research and development in both semiconductor and advanced packaging is a unique opportunity for the United States given how the lines are blurring between these areas,” said Under Secretary of Commerce for Standards and Technology and National Institute of Standards and Technology Director Laurie Locascio. “Ensuring development in both areas is well synchronized will be key for future advancements in AI and other technologies. These facilities will lower barriers to participation in semiconductor research and innovation and will provide state-of-the-art tools and processes at a scale that allows for more rapid transition to manufacturing.”
“This announcement represents a major step forward in the evolution of the NSTC and will provide key capabilities for researchers in the United States to accelerate the rate and pace of domestic R&D. These facilities will convene the semiconductor ecosystem to enable a vibrant and sustainable innovation pipeline,” said Deirdre Hanford, CEO of Natcast, the operator of the NSTC.
Update 12-07-24
The plan is for the the NSTC Administrative and Design Facility to be operational in 2025, the NSTC EUV Centre by 2026, and the NSTC Prototyping and NAPMP Advanced Packaging Piloting Facility in 2028.
The NSTC Prototyping and NAPMP Advanced Packaging Piloting Facility will combine state-of-the-art manufacturing and packaging and next-generation technology development to provide NSTC members and NAPMP funded researchers with 300mm research, prototyping, and packaging capabilities. Co-locating the NSTC research and development prototyping and NAPMP packaging capabilities in a single facility will provide the domestic semiconductor ecosystem with unique value to conduct collaborative semiconductor and advanced packaging research.
The NSTC Administrative and Design Facility will be a multi-functional facility, serving as the location for key operations of the NSTC, including: hosting Natcast administrative functions, convening consortium members and conducting NSTC programmatic activity such as the Workforce Center of Excellence, NSTC Design Enablement Gateway, and advanced semiconductor research in chip design, electronic design automation, chip and system architecture, and hardware security.
The NSTC EUV Center will provide NSTC members with access to EUV technology to facilitate a wider range of research and a path to commercialization, including technologies with the most challenging feature sizes. Next-generation technology development requires access to EUV lithography. In addition to access to EUV technology, this center will also provide appropriate space for Natcast researchers and staff as well as member assignees to conduct research and collaborate in the facility.
www.nist.gov/chips/chips-RD-funding-opportunities
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