£1.7m for new transistor technology in clean energy
A new transistor technology that could replace CMOS has received £1.7m (€2m) from the UK government for further development of clean energy applications on low cost process technology.
We covered the Bizen transistor technology being developed by Nottingham startup Search for the Next (SFN) back in October last year. Compared to CMOS, the quantum tunnelling approach used by Bizen halves the number of layers needed to make a chip and reduces the production time from 15 weeks to just three weeks. The process also provides a three-fold increase in gate density that shrinks the die size with a similar speedd and power consumption. The technology has been used in a pilot project with Semefab in Scotland, and we talked to the CEO there about it. First test chips are planned for this summer:
The grant has been made by the ‘Driving the Electric Revolution Challenge’ program, part of UKRI’s Industrial Strategy Challenge Fund. The focus of the clean energy fund is on the global transition to clean energy technologies and electrification, helping businesses across numerous sectors including transport, energy, construction and agriculture. SFN is one of more than 30 partner research and technology organisations that will collaborate in four new Industrialisation Centres:
“We are extremely pleased that the UK government has recognised the key role that Bizen will play in enabling the UK to meet its ambitious net zero targets. Bizen has the ability to enable the UK to develop a leadership position in semiconductor manufacturing. My challenge to industry is this: have a look at Bizen and we are sure that you’ll see that it’s impossible to produce a wide variety of ICs at a lower cost or on a shorter time to market,” said David Summerland, CEO of SFN (above).
The number of layers needed for a Bizen device range from four to eight for devices supporting low to high voltage operation, compared with ten to seventeen for CMOS. Using Bizen, power consumption drops, the size drops and the integration and speed increases, allowing complex devices to be manufactured in the legacy fabs with large process geometry in the UK for clean energy applications, says Summerland. This compares to the increasing cost of CMOS moving from 7nm to 5nm process nodes.
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