100G Ethernet packet parser reference design kit using Tabula’s ABAX2P1 3PLD
The 100 GbE packet parser represents a novel approach to this class of network functions, delivering a unique combination of programmability and low latency currently not achievable on a programmable device. It provides support for multiple L2 accesses and trunk frame formats and is easily scalable to support L3 and L4 parsing. It also benefits from a very small footprint – less than 2K LUTs for a single 100G stream, making it an extremely cost-effective and power-efficient programmable solution that can be extended to support multiple 100G streams on a single chip.
Tabula’s Spacetime architecture enables designers to co-optimize performance and density. Combining programmable fabric in which all components can operate at 2 GHz with multi-port high-performance memories, this unique architecture opens the doors to design solutions that could not be explored before. In this 100 GbE packet parser reference design, these capabilities are used to parallelize the processing of multiple fields of an entire 100 GbE packet header, enabling the parsing function to be completed in a record 17ns latency and making the parser software configurable to handle different L2 formats or extended to L3 and L4 parsing. It supports 149M packets/s at the minimum packet size of 64 bytes, with a guaranteed bandwidth of 122Gbps while drawing less than 1.5 Watts per 100 GbE stream.
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