112 Gbps SerDes validated in 7nm FinFET for next-gen FPGAs
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eeNews Europe
Fabricated on TSMC’s 7nm FinFET process technology, these 112 Gbps SerDes provide multi-standard support for a wide range of digital serial communications standards with data rates ranging from 1 Gbps to 112 Gbps.
The results from the 112 Gbps SerDes validation chip show that the transmitter generates clean eye diagrams and exhibits excellent linearity, jitter, and signal-to-noise and distortion ratio (SNDR) with sharp rise and fall times at multiple data rates up to the SerDes’ maximum rate of 112 Gbps. The SerDes’ receivers employ advanced DSP techniques including constant modulus algorithm (CMA) adaptive equalisation and decision-based adaptation to deliver the best possible receiver performance at low power.
Achronix – www.achronix.com
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