13 Mpixel CMOS image sensor maximises sensitivity: and stacked-dice sensors
ON Semiconductor’s next-generation 13 megapixel (MP) image sensor, the AR1335 is based on 1.1 micron (µm) pixel technology; it sets a new benchmark in sensitivity along with increases in quantum efficiency (QE) and linear full well capacity. Designed specifically for smartphone camera applications, this image sensor delivers near-digital-still-camera quality with power consumption and footprint that are optimised for mobile devices.
ON Semiconductor has developed its 1.1 µm pixel technology for performance smartphone sensors with pixel and colour filter array (CFA) processing advancements, which has increased the sensitivity by nearly 20% compared to the previous generation. Image quality is significantly improved, especially in low light. 13-MP resolution supports high-quality zoom, and sharp reproduction of scene details. Professional quality video is supported thorough 4K Ultra-High Definition (UHD) and Cinema formats at 30 frames per second (fps) and Full HD 1080P at 60 fps. The high 32-degree Chief Ray Angle (CRA) supports low z-height applications.
The AR1335 is in mass production in die format and has been designed into several smartphone models with availability in leading phones expected by the second quarter of 2015.
Die-stacked sensors
In a related field, ON has disclosed advances in high efficiency 3D sensor stacking technology, which it says can deliver improved power, performance and size efficiency for future sensors for mobile and consumer applications.
The company has characterised and demonstrated its first fully-functional stacked CMOS imaging sensor featuring a smaller die footprint, higher pixel performance and better power consumption compared to traditional monolithic non-stacked designs. The technology has been successfully implemented and characterised on a test chip with 1.1-micron (µm) pixels and will be introduced in a product later this year.
Conventional sensor designs in a monolithic substrate process require separate die area to support both the pixel array and supporting circuitry. With 3D stacking technology, the pixel array and the supporting circuitry are manufactured on separate substrates and then stacked with connections between the two made with through silicon vias (TSVs). This allows the pixel array to overlay the underlying circuitry and result in a more efficient die floorplan. With this approach, design engineers can optimise each part of the sensor for imaging performance, cost, power and die size. With the optimisation of the pixel array, sensors can have improved pixel performance with lower noise levels and enhanced pixel response. The underlying circuitry can use more aggressive design rules to lower power consumption. The smaller overall footprint supports today’s advanced camera modules that integrate Optical Image Stabilisation (OIS) and additional data storage in the same module footprint.
ON Semiconductor; www.onsemi.com
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